1. Technical Field
Various embodiments of the present disclosure relate generally to nonvolatile memory cells and, more particularly, to nonvolatile memory cells having a lateral coupling structure and nonvolatile memory cell arrays including the same.
2. Related Art
Electrically erasable programmable read only memory (EEPROM) devices and flash memory devices belong to nonvolatile memory (NVM) devices that retain their stored data even when their power supplies are interrupted. Various memory cell structures of the NVM devices have been proposed to improve their performance. A typical unit memory cell of the NVM devices employs a stack gate structure including a floating gate, an inter-gate dielectric layer and a control gate which are sequentially stacked on a semiconductor substrate. As electronic systems become smaller with the development of fabrication techniques for semiconductor devices, system-on-chip (SOC) products have been developed and utilized as important devices for high performance digital systems. Each of the SOC products may include a plurality of semiconductor devices executing various functions in a single chip. For example, the SOC product may include at least one logic device and at least one memory device which are integrated into a single chip. Thus, fabrication technologies for embedded NVM devices may be required to embed the NVM devices into the SOC products.
To embed the NVM devices in the SOC products, the process technology of the NVM devices has to be compatible with the process technology of the logic device included in the SOC products. In general, the logic devices employ transistors having a single gate structure, whereas the NVM devices employ cell transistors having a stack gate structure that is, a double gate structure. Thus, the SOC products including the NVM devices and the logic devices may require a complicated process technology. Accordingly, single-layered gate NVM devices employing a single-layered gate cell structure are very attractive as a candidate for the embedded NVM devices. That is, complementary metal-oxide-semiconductor (CMOS) circuits of the logic devices may be readily realized using a process technology of the single-layered gate NVM devices. As a result, the process technology of the single-layered gate NVM devices may be widely used in fabrication of the SOC products including the embedded NVM devices.